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HD61202U
(Dot Matrix Liquid Crystal GraphicDisplay Column Driver)
Description
HD61202U is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display to provide more flexible than character display. As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic displays with many dots. The HD61202U, which is produced in the CMOS process, can complete portable battery drive equipment in combination with a CMOS micro-controller, utilizing the liquid crystal display's low power dissipation. Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination with the row (common) driver HD61203U.
Features
* Dot matrix liquid crystal graphic display column driver incorporating display RAM * RAM data direct display by internal display RAM RAM bit data 1: On RAM bit data 0: Off * Internal display RAM address counter preset, increment * Display RAM capacity: 512 bytes (4096 bits) * 8-bit parallel interface * Internal liquid crystal display driver circuit: 64 * Display duty cycle Drives liquid crystal panels with 1/32-1/64 duty cycle multiplexing
816
HD61202U
* Wide range of instruction function Display data read/write, display on/off, set address, set display start line, read status * Lower power dissipation: during display 2 mW max * Power supply: VCC: 2.7V~5.5V * Liquid crystal display driving voltage: 8V to 16V * CMOS process
Ordering Information
Type No. HD61202UFS HD61202UTE HCD61202U Package 100-pin plastic QFP (FP-100A) 100-pin thin plastic QFP (TFP-100B) Chip
817
HD61202U
Pin Arrangement
FRM E o1 o2 CL D/I R/W RST CS1 CS2 CS3 NC NC NC DB7 DB6 DB5 DB4 DB3 DB2 ADC M VCC V4R V3R V2R V1R VEE2 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 Y47 Y46 Y45 Y44 Y43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61202UFS (FP-100A)
818
Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DB1 DB0 GND V4L V3L V2L V1L VEE1 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22
(Top view)
HD61202U
M ADC FRM E o1 o2 CL D/I R/W RST NC CS1 NC CS2 CS3 NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND VCC V4R V3R V2R V1R VEE2 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 Y47 Y46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61202UTE (TFP-100B)
Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V4L V3L V2L Y1L VEE1 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
(Top view)
819
HD61202U
HCD61202U PAD Arrangement
No.1 NO.78
NO.3 Chip Size CHIP CODE HD61202U NO.27 NO.54 Coordinate Origin Pad Size
: 4.08 x 4.08 mm2 : Pad Center : Chip center : 90 x 90 m2
No.28
No.53
HCD61202U Pad Location Coordinates
Coordinate PAD PAD No. Name X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ADC M VCC V4R V3R V2R V1R VEE2 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 -1493 -1649 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 -1789 1756 1756 1689 1445 1293 1148 1011 869 721 591 461 331 201 71 -60 -190 -320 -450 -580 -710 -840 -970 Coordinate PAD PAD Y No. Name X 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Y47 Y46 Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 -1789 -1508 -1789 -1653 -1764 -1789 -1604 -1789 -1452 -1789 -1312 -1789 -1171 -1789 -976 -1789 -846 -1789 -716 -1789 -586 -1789 -456 -1789 -326 -1789 -196 -1789 -65 -1789 65 -1789 195 -1789 325 -1789 455 -1789 585 -1789 715 -1789 845 -1789 975 -1789 1170 -1789 1311 -1789 PAD PAD No. Name 51 Y22 52 Y21 53 Y20 54 Y19 55 Y18 56 Y17 57 Y16 58 Y15 59 Y14 60 Y13 61 Y12 62 Y11 63 Y10 64 Y9 65 66 67 68 69 Y8 Y7 Y6 Y5 Y4 Coordinate X Y 1452 -1789 1604 -1789 1764 -1789 1789 -1654 1789 -1507 1789 -1369 1789 -1230 1789 -1100 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 1789 -970 -840 -710 -580 -450 -320 -190 -60 71 201 331 461 591 721 1024 1153 1293 Coordinate PAD PAD Y No. Name X 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 V3L V4L GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 NC NC NC CS3 CS2 CS1 RST R/W D/I CL o2 o1 E 218 62 -94 -249 -405 -560 -716 -871 -1027 -1182 1756 1756 1756 1756 1756 1756 1756 1756 1756 1756 1756 1789 1789 1789 1495 1335 1176 1016 854 694 535 375 1442 1590 1756 1756 1756 1756 1756 1756 1756 1756 1756
70 Y3 71 Y2 72 Y1 73 VEE1 74 75 V1L V2L
-1789 -1100 -1789 -1230 -1789 -1369
FRM -1338
820
Block Diagram
VCC GND VEE1 VEE2 M ADC
Interface control
9 9
XY address counter
V1L V2L V3L V4L
Instruction register
3 8 4096 bit 8 6 Z address counter 6 6 Display start line register Display on/off Display data RAM
Input register
8
1 2 3
1 2 3
Y1 Y2 Y3
I/O buffer
CS1, CS2, CS3 R/W D/I E DB0-DB7 8 8 Output register Busy flag
Liquid crystal display driver circuit
62 63 64
Display data latch 64
64
62 63 64
Y62 Y63 Y64
V1R V2R V3R V4R CL FRM
RST o1 o2
HD61202U
821
HD61202U
Terminal Functions
Terminal Name VCC GND Number of Terminals 2 I/O Connected to Power supply Functions Power supply for internal logic. Recommended voltage is: GND = 0V VCC = 2.7 to 5.5V VEE1 VEE2 2 Power supply Power supply for liquid crystal display drive circuit. Recommended power supply voltage is VCC-VEE = 8 to 16V. Connect the same power supply to VEE1 and VEE2. VEE1 and VEE2 are not connected each other in the LSI. 8 Power supply Power supply for liquid crystal display drive. Apply the voltage specified depending on liquid crystals within the limit of VEE through VCC. V1L (V1R), V2L (V2R): Selection level V3L (V3R), V4L (V4R): Non-selection level Power supplies connected with V1L and V1R (V2L & V2R, V3L & V3R, V4L & V4R) should have the same voltages.
V1L, V1R V2L, V2R V3L, V3R V4L, V4R
$ $
CS3
3
I
MPU
Chip selection. Data can be input or output when the terminals are in the following conditions: Terminal name Condition
$
L
$
L
CS3 H
E
1
I
MPU
Enable. At write (R/W = low): Data of DB0 to DB7 is latched at the fall of E. At read (R/W = high): Data appears at DB0 to DB7 while E is at high level.
R/W
1
I
MPU
Read/write. R/W = High: Data appears at DB0 to DB7 and can be read by the MPU. When E = high, $, $ = low and CS3 = high. R/W = Low: DB0 to DB7 can accept at fall of E when $, $ = low and CS3 = high.
D/I
1
I
MPU
Data/instruction. D/I = High: Indicates that the data of DB0 to DB7 is display data. D/I = Low: Indicates that the data of DB0 to DB7 is display control data.
822
HD61202U
Terminal Name ADC Number of Terminals 1 I/O I Connected to VCC/GND Functions Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. ADC = High: Y1: H'0, Y64: H'63 ACD = Low: Y64: H'0, Y1: H'63 DB0-DB7 M FRM 8 1 1 I/O I I MPU HD61203U HD61203U Data bus, three-state I/O common terminal. Switch signal to convert liquid crystal drive waveform into AC. Display synchronous signal (frame signal). Presets the 6-bit display line counter and synchronizes the common signal with the frame timing when the FRM signal becomes high. CL 1 I HD61203U Synchronous signal to latch display data. The rising CL signal increments the display output address counter and latches the display data. 2-phase clock signal for internal operation. The o1 and o2 clocks are used to perform operations (I/O of display data and execution of instructions) other than display. Y1-Y64 64 O Liquid crystal display Liquid crystal display column (segment) drive output. The outputs at these pins are at the light-on level when the display RAM data is 1, and at the light-off level when the display RAM data is 0. Relation among output level, M, and display data (D) is as follows:
M 1 0
o1, o2
2
I
HD61203U
D Output level
1
0
1
0
V1 V3 V2 V4
#$%
1
I
MPU or external CR
The following registers can be initialized by setting the #$% signal to low level. 1. On/off register 0 set (display off) 2. Display start line register line 0 set (displays from line 0) After releasing reset, this condition can be changed only by instruction.
NC
Unused terminals. Don't connect any lines to these terminals. Note: 1 corresponds to high level in positive logic.
3
Open
823
HD61202U
Function of Each Block
Interface Control I/O Buffer: Data is transferred through 8 data bus lines (DB0-DB7). DB7: MSB (most significant bit) DB0: LSB (least significant bit) Data can neither be input nor output unless $ to CS3 are in the active mode. Therefore, when $ to CS3 are not in active mode it is useless to switch the signals of input terminals except #$% and ADC; that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention to #$% and ADC which operate irrespectively of $ to CS3. Register: Both input register and output register are provided to interface to an MPU whose speed is different from that of internal operation. The selection of these registers depend on the combination of R/W and D/I signals (Table 1). 1. Input register The input register is used to store data temporarily before writing it into display data RAM. The data from MPU is written into input register, then into display data RAM automatically by internal operation. When $ to CS3 are in the active mode and D/I and R/W select the input register as shown in Table 1, data is latched at the fall of the E signal. 2. Output register The output register is used to store data temporarily that is read from display data RAM. To read out the data from the output register, $ to CS3 should be in the active mode and both D/I and R/W should be 1. With the read display data instruction, data stored in the output register is output while E is high level. Then, at the fall of E, the display data at the indicated address is latched into the output register and the address is increased by 1. The contents in the output register are rewritten by the read display data instruction, but are held by address set instruction, etc. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address is set, but can be output at the second read of data. That is to say, one dummy read is necessary. Figure 1 shows the MPU read timing. Table 1
D/I 1 1 0 0
Register Selection
R/W 1 0 1 0 Operation Reads data out of output register as internal operation (display data RAM output register) Writes data into input register as internal operation (input register display data RAM) Busy check. Read of status data. Instruction
824
HD61202U
Busy Flag Busy flag = 1 indicates that HD61202U is operating and no instructions except status read instruction can be accepted. The value of the busy flag is read out on DB7 by the status read instruction. Make sure that the busy flag is reset (0) before issuing instructions.
D/I R/W E Address Output register DB0-DB7 Busy check Write address N Busy check Read data (dummy) N N+1 Data at address N Busy check Read data at address N N+2 Data at address N + 1 Busy check Data read address N+1
Figure 1 MPU Read Timing
E
Busy flag T Busy fCLK is o1, o2 frequency 1/fCLK T Busy 3/fCLK
Figure 2 Busy Flag
825
HD61202U
Display On/Off Flip/Flop The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on state, the display data corresponding to that in RAM is output to the segments. On the other hand, the display data at all segments disappear in off state independent of the data in RAM. It is controlled by display on/off instruction. #$% signal = 0 sets the segments in off state. The status of the flip/flop is output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To control display data latch by this flip/flop, CL signal (display synchronous signal) should be input correctly. Display Start Line Register The display start line register specifies the line in RAM which corresponds to the top line of LCD panel, when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen. 6-bit display start line information is written into this register by the display start line set instruction. When high level of the FRM signal starts the display, the information in this register is transferred to the Z address counter, which controls the display address, presetting the Z address counter. X, Y Address Counter A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3 bits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions. 1. X address counter Ordinary register with no count functions. An address is set by instruction. 2. Y address counter An Address is set by instruction and is increased by 1 automatically by R/W operations of display data. The Y address counter loops the values of 0 to 63 to count. Display Data RAM Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data = 0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can be reversed by ADC signal. As the ADC signal controls the Y address counter, reversing of the signal during the operation causes malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect ADC pin to VCC or GND when using. Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and ADC = 0 (display start line = 0, 1/64 duty cycle).
826
HD61202U
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 (HD61203U X1) (HD61203U X2) (HD61203U X3) (HD61203U X4) (HD61203U X5) (HD61203U X6) (HD61203U X7) (HD61203U X8) (HD61203U X9)
LCD display pattern
COM62 COM63 COM64 YY 62 63 Y64
0 0 1 0 0 0 0 0 0 001 001 001 101 011 001 001 000 000
(HD61203U X62) (HD61203U X63) (HD61203U X64)
Y1 Y2Y3 Y4 Y5 Y6 Line 0 Line 1 Line 2 X=0 Display RAM data
011100 100010 100010 100010 111110 100010 100010 000000 000000
HD61202U pin name DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB)
X=1
1 01000 11111 00000 0 0 0 000 000 000
X=7 Line 62 Line 63
012345
61 62 63 ADC = 1 (connected to VCC)
RAM Y address
Figure 3 Relation between RAM Data and Display
827
HD61202U
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 (HD61203U X1) (HD61203U X2) (HD61203U X3) (HD61203U X4) (HD61203U X5) (HD61203U X6) (HD61203U X7) (HD61203U X8) (HD61203U X9)
LCD display pattern
COM62 COM63 COM64 YYYY 64 63 62 61 Line 0 Line 1 Line 2 X=0 Display RAM data Y 59
0 0 1 0 0 0 0 0 0
(HD61203U X62) (HD61203U X63) (HD61203U X64)
Y3 Y2 Y1
001 001 001 101 011 001 001 000 000
011100 100010 100010 100010 111110 100010 100010 000000 000000
HD61202U pin name DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB)
X=1
1 010000 111110 000000 000 000 000
X=7 Line 62 Line 63
012345
61 62 63 ADC = 0 (connected to GND)
RAM Y address
Figure 3 Relation between RAM Data and Display (cont)
828
HD61202U
Z Address Counter The Z address counter generates addresses for outputting the display data synchronized with the common signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high level of FRM, the contents of the display start line register is present at the Z counter. Display Data Latch The display data latch stores the display data temporarily that is output from display data RAM to the liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction controls the data in this latch and does not influence data in dicsplay data RAM. Liquid Crystal Display Driver Circuit The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels, V1, V2, V3, and V4 to be output. Reset The system can be initialized by setting #$% terminal at low level when turning power on. 1. Display off 2. Set display start line register line 0. While #$% is low level, no instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in Table 2. Table 2
Item Reset time
Power Supply Initial Conditions
Symbol tRST Min 1.0 Typ -- Max -- Unit s
Do not fail to set the system again because RESET during operation may destroy the data in all the registers except on/off register and in RAM.
tRST
RST VILC Reset timing
829
HD61202U
Display Control Instructions
Outline Table 3 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals from the MPU. These explanations are detailed in the following pages. Generally, there are following three kinds of instructions: 1. Instruction to set addresses in the internal RAM 2. Instruction to transfer data from/to the internal RAM 3. Other instructions In general use, the second type of instruction is used most frequently. Since Y address of the internal RAM is increased by 1 automatically after writing (reading) data, the program can be shortened. During the execution of an instruction, the system cannot accept instructions other than status read instruction. Send instructions from MPU after making sure that the busy flag is 0, which is proof that an instruction is not being executed.
830
Table 3
Instructions
Code Instructions Display on/off Display start line Set page (X address) Set Y address Status read 1 0 Busy 0 ON/ OFF Reset 0 0 0 0 0 0 0 1 Y address (0-63) 0 0 1 0 1 1 1 Page (0-7) 0 0 1 1 Display start line (0-63) 0 0 0 0 1 1 1 1 1 1/0 R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Functions Controls display on/off. RAM data and internal status are not affected. 1: on, 0: off. Specifies the RAM line displayed at the top of the screen. Sets the page (X address) of RAM at the page (X address) register. Sets the Y address in the Y address counter. Reads the status. RESET 1: Reset 0: Normal ON/OFF 1: Display off 0: Display on Busy Write display data 0 1 Write data 1: Internal operation 0: Ready Writes data DB0 (LSB) to DB7 (MSB) on the data bus into display RAM. Reads data DB0 (LSB) to DB7 (MSB) from the display RAM to the data bus.
Read display data
1
1
Read data
Has access to the address of the display RAM specified in advance. After the access, Y address is increased by 1.
Note: Busy time varies with the frequency (fCLK) of o1, and o2. (1/fCLK TBUSY 3/fCLK)
HD61202U
831
HD61202U
Detailed Explanation Display On/Off
R/W D/I DB7 Code 0 0 0 MSB 0 1 1 1 1 1 DB0 D LSB
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1. Display Start Line
R/W D/I DB7 Code 0 0 1 MSB 1 A A A A A DB0 A LSB
Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed at the top of the screen. Figure 4 shows examples of display (1/64 duty cycle) when the start line = 0-3. When the display duty cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. Set Page (X Address)
R/W D/I DB7 Code 0 0 1 MSB 0 1 1 1 A A DB0 A LSB
X address AAA (binary) of the display data RAM is set in the X address register. After that, writing or reading to or from MPU is executed in this specified page until the next page is set. See Figure 5. Set Y Address
R/W D/I DB7 Code 0 0 0 MSB 1 A A A A A DB0 A LSB
Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Y address counter is increased by 1 every time the data is written or read to or from MPU.
832
HD61202U
Status Read
R/W D/I DB7 Code 1 0 Busy MSB 0 ON/ OFF RESET 0 0 0 DB0 0 LSB
* Busy When busy is 1, the LSI is executing internal operations. No instructions are accepted while busy is 1, so you should make sure that busy is 0 before writing the next instruction. * ON/OFF Shows the liquid crystal display conditions: on condition or off condition. When on/off is 1, the display is in off condition. When on/off is 0, the display is in on condition. * RESET RESET = 1 shows that the system is being initialized. In this condition, no instructions except status read can be accepted. RESET = 0 shows that initializing has finished and the system is in the usual operation condition.
833
HD61202U
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
COM60 COM61 COM62 COM63 COM64 Start line = 0
COM60 COM61 COM62 COM63 COM64 Start line = 1
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
COM60 COM61 COM62 COM63 COM64 Start line = 2
COM60 COM61 COM62 COM63 COM64 Start line = 3
Figure 4 Relation between Start Line and Display
834
HD61202U
Write Display Data
R/W D/I DB7 Code 0 1 D MSB D D D D D D DB0 D LSB
Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1 automatically. Read Display Data
R/W D/I DB7 Code 1 1 D MSB D D D D D D DB0 D LSB
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1 automatically. One dummy read is necessary right after the address setting. For details, refer to the explanation of output register in "Function of Each Block".
Y address 012 DB0 to DB7 DB0 to DB7 Page 0 61 62 63 X=0
Page 1
X=1
DB0 to DB7 DB0 to DB7
Page 6
X=6
Page 7
X=7
Figure 5 Address Configuration of Display Data RAM
835
HD61202U
Use of HD61202U
Interface with HD61203 (1/64 Duty Cycle)
Rf R VCC V1 V6 V5 V2 VEE VCC Cf CR C X1 COM1 LCD panel 64 x 64 dots SEG1 X64 COM64 SEG64 Y64 VCC V1L, V1R V2L, V2R V3L, V3R V4L, V4R VEE1, VEE2 GND VCC V1 V2 V3 V4 VEE
VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND
HD61203U SHL DS1 DS2 TH CL1 FS M/S FCS STB DL DR Open Open Y1 M CL2 FRM o1 o2 M CL FRM o1 o2 HD61202U
Power supply circuit +5V (VCC) R3 V1 R1 R1 R2 R1 R1
- + - + - + - +
VCC
ADC RST
R3 V6 R3 R3 V3 V4 R3 V5 R3 V2 VEE External CR
R3 = 15
-10V
Contrast
836
CS1 CS2 CS3 R/W D/I E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 MPU
HD61202U
o1 o2 1 2 3 48 49
Input CL FRM M 1 frame 1 frame V1 V6 X1 V5 V2 V1 V6 COM X2 V5 V2 V1 V6 X64 V5 V2 V5 V1 V6 V6 V5 V5 V6 V5 V2 64 1 2 3 64 1 2 3 64 1
V1 V3 Y1 SEG Y64 V4 Selected V4 V2 V1 V3 Non-selected V4 V2 V4
V1
V1
The waveforms of Y1 to Y64 outputs vary with the display data. In this example, the top line of the panel lights up and other dots do not.
Figure 6 LCD Driver Timing Chart (1/64 Duty Cycle)
837
HD61202U
Interface with CPU
1. Example of Connection with H8/536/S
Decoder A15 to A1 AS CS1 CS2 CS3
VCC
A R/W H8/536S E D0 to D7 VCC RES
D/I R/W HD61202U E DB0 to DB7 RST
Figure 7 Example of Connection with H8/536S
838
HD61202U
2. Example of Connection with HD6801 * Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus. * 74LS154 4-to-16 decoder generates chip select signal to make specified HD61202U active after decoding 4 bits of P10 to P13. * Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write from/to the external memory area ($0100 to $01FE) to control HD61202U. In this case, IOS signal is output from SC1 and R/W signal from SC2. * For details of HD6800 and HD6801, refer to their manuals.
74LS154 P10 P11 P12 P13 (IOS) (SC1) (R/W) (SC2) HD6801 P14 E P30 (Data bus) P37 A Y0 B Y1 C Y15 D G1 G2 CS1 CS2 CS3
VCC
R/W D/I E DB0 HD61202U No. 1
DB7
Figure 8 Examples of Connection with HD6801
839
HD61202U
Example of Application In this example, two HD61203s output the equivalent waveforms. So, stand-alone operation is possible. In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ..., and COM64 and COM128 to X64. However, for the large screen display, it is better to drive in 2 rows as in this example to guarantee the display quality.
HD61202U HD61202U No. 9 No. 10 Y1 Y64 Y1 Y64
HD61202U No. 16 Y1 Y32
COM1 COM2 COM3 X1 X2 X3 X64 COM64 LCD panel 128 x 480 dots
HD61203U (master)
HD61203U (slave)
X1 X2 X3 X64
COM65 COM66 COM67
COM128
Y1
Y64
Y1
Y64
Y1
Y32
HD61202U No. 1
HD61202U No. 2
HD61202U No. 8
Figure 9 Application Example
840
HD61202U
Absolute Maximum Ratings
Item Supply voltage Symbol VCC VEE1 VEE2 Terminal voltage (1) Terminal voltage (2) Operating temperature Storage temperature VT1 VT2 Topr Tstg Value -0.3 to +7.0 VCC - 17.0 to VCC + 0.3 VEE - 0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -20 to +75 -55 to +125 Unit V V V V C C Note 2 3 4 2, 5
Notes: 1. LSIs may be destroyed if they are used beyond the absolute maximum ratings. In ordinary operation, it is desirable to use them within the recommended operation conditions. Useing them beyond these conditions may cause malfunction and poor reliability. 2. All voltage values are referenced to GND = 0V. 3. Apply the same supply voltage to VEE1 and VEE2. 4. Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R. Maintain VCC V1L = V1R V3L = V3R V4L = V4R V2L = V2R VEE 5. Applies to M, FRM, CL, #$%, ADC, o1, o2, $, $, CS3, E, R/W, D/I, and DB0-DB7.
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HD61202U
Electrical Characteristics (GND = 0V, VCC = 2.7 ~ 5.5V, VCC - VEE = 8.0 to 16.0V, Ta = -20 ~ +75C)
Limit Item Input high voltage Symbol VIHC VIHT Input low voltage VILC VILT Output high voltage VOH Min 0.7VCC 0.7VCC 2.0 0.0 0.0 0.0 0.75VCC 2.4 Output low voltage VOL -- -- Input leakage current IIL Three-state (off) input current Liquid crystal supply leakage current Driver on resistance Dissipation current ITSL ILSL RON ICC (1) ICC (2) Notes: 1. 2. 3. 4. 5. 6. 7. -1 -5 -2 -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- Max VCC VCC VCC 0.3VCC 0.5 0.8 -- -- 0.2VCC 0.4 1 5 2 7.5 100 500 Unit V V V V V V V V V V A A A k A A Test Condition VCC = 2.7V~5.5V VCC = 2.7V~4.5V VCC = 4.5V~5.5V VCC = 2.7V~5.5V VCC = 2.7V~4.5V VCC = 4.5V~5.5V IOH = -100 A, VCC = 2.7V~4.5V IOH = -205 A VCC = 4.5V~5.5V IOL = 100 uA, VCC = 2.7V~4.5V IOL = 1.2mA, VCC = 4.5V~5.5V Vin = GND ~ VCC Vin = GND ~ VCC Vin = VEE-VCC ILOAD = 0.1 mA, VCC-VEE = 15V During display During access, Cycle = 1MHz Notes 1 2 2 1 2 2 3 3 3 3 4 5 6 8 7 7
Applies to M, FRM, CL, RST, o1, and o2. Applies to CS1, CS2, CS3, E, R/W, D/I, and DB0-DB7. Applies to DB0-DB7. Applies to terminals except for DB0-DB7. Applies to DB0-DB7 at high impedance. Applies to V1L-V4L and V1R-V4R. Specified when LCD is in 1/64 duty cycle mode. Operation frequency: fCLK = 250 kHz (o1 and o2 frequency) Frame frequency: fM = 70 Hz (FRM frequency) Specified in the state of Output terminal: Not loaded Input level: VIH = VCC (V) VIL = GND (V) Measured at VCC terminal
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HD61202U
8. Resistance between terminal Y and terminal V (one of V1L, V1R, V2L, V2R, V3L, V3R, V4L, and V4R) when load current flows through one of the terminals Y1 to Y64. This value is specified under the following condition:
VCC-VEE = 15.0V V1L = V1R, V3L = V3R = VCC-2/7 (VCC-VEE) V2L = V2R, V4L = V4R = VCC+2/7 (VCC-VEE) RON V1L, V1R V3L, V3R V4L, V4R V2L, V2R Terminal Y (Y1-Y64)
The following is a description of the range of power supply voltage for liquid crystal display drive. Apply positive voltage to V1L = V1R and V3L = V3R and negative voltage to V2L = V2R and V4L = V4R within the AEV range. This range allows stable impedance on driver output (RON). Notice that AEV depends on power supply voltage VCC-VEE.
VCC V1 (V1L = V1R) V V3 (V3L = V3R) 5.0 Range of power supply voltage for liquid crystal display drive
V (V) V V4 (V4L = V4R) V2 (V2L = V2R) VEE
3
8 VCC-VEE (V)
16
Correlation between driver output waveform and power supply voltages for liquid crystal display drive
Correlation between power supply voltage VCC-VEE and V
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HD61202U
Terminal Configuration
Input Terminal VCC PMOS Applicable terminals: M, FRM, CL, RST, o1, o2, CS1, CS2, CS3, E, R/W, D/I, ADC
NMOS
Input/Output Terminal
VCC (Input circuit) PMOS VCC
Applicable terminals: DB0-DB7
Enable NMOS PMOS Data NMOS (Output circuit) [three state] Output Terminal Applicable terminals: Y1-Y64 V1L, V1R
PMOS VCC PMOS VCC NMOS VEE NMOS VEE
V3L, V3R
V4L, V4R
V2L, V2R
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HD61202U
Interface AC Characteristics MPU Interface (GND = 0V, VCC = 2.7 to 5.5V, Ta = -20 to +75C)
Item E cycle time E high level width E low level width E rise time E fall time Address setup time Address hold time Data setup time Data delay time Data hold time (write) Data hold time (read) Symbol tCYC PWEH PWEL tr tf tAS tAH tDSW tDDR tDHW tDHR Min 1000 450 450 -- -- 140 10 200 -- 10 20 Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- -- 320 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns Fig. 10 Fig. 11, Fig. 12 Fig. 10 Fig. 11 Note Fig. 10, Fig. 11
tCYC E VIHT VILT PWEL tr R/W VIHT VILT VIHT VILT tDSW DB0-DB7 VIHT VILT tDHW tAS tAS CS1-CS3 D/I tAH PWEH tf tAH
Figure 10 MPU Write Timing
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HD61202U
tCYC E PWEL tr R/W VIHT VILT VIHT VILT tDDR DB0-DB7 VIHT VILT tDHR tAS tAS CS1-CS3 D/I tAH tAH PWEH tf
Figure 11 MPU Read Timing
VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V
VCC = 5V 2.4k
D1 Test point 90pF 11k
Test point Diodes IS2074 H 50pF
Notes) including jip capacitance
Figure 12 DB0-DB7: Load Circuit
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HD61202U
Clock Timing (GND = 0V, VCC = 2.7 to 5.5V, Ta = -20 to +75C)
Limit Item o1, o2 cycle time o1 low level width o2 low level width o1 high level width o2 high level width o1-o2 phase difference o2-o1 phase difference o1, o2 rise time o1, o2 fall time Symbol tcyc tWLo1 tWLo2 tWHo1 tWHo2 tD12 tD21 tr tf Min 2.5 625 625 1875 1875 625 625 -- -- Typ -- -- -- -- -- -- -- -- -- Max 20 -- -- -- -- -- -- 150 150 Unit s ns ns ns ns ns ns ns ns Test Condition Fig. 13
tcyc tf VIHC VILC tr tWHo1
o1
tWLo1
tD12
tD21
o2
VIHC VILC tf tWLo2 tr tcyc
tWHo2
Figure 13 External Clock Waveform
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HD61202U
Display Control Timing (GND = 0V, VCC = 2.7 to 5.5V, Ta = -20 to +75C)
Limit Item FRM delay time M delay time CL low level width CL high level width Symbol tDFRM tDM tWLCL tWHCL Min -2 -2 35 35 Typ -- -- -- -- Max +2 +2 -- -- Unit s s s s Test Condition Fig. 14
CL
VIHC VILC tDFRM
tWLCL tWHCL
tDFRM
FRM
VIHC VILC tDM VIHC VILC
M
Figure 14 Display Control Signal Waveform
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